1. Field of the Invention
The present invention relates to a method of employing a semiconductor memory system in the storage and readout of video signal data, and more particularly to a technique utilizing first and second FIFO memories of the memory system in a tandem manner to perform various video-related operations in a plurality of function modes.
2. Description of the Prior Art
With semiconductor memories having been manufactured at lower prices and with the development of digital processing techniques with respect to video signals, home TVs, VTRs and appliances with built-in semiconductor controls operated with digital signals are becoming available. Video signals as input into a TV and a VTR, with special regard to the image display (consisting of a Brown tube and a cathode electronic gun), must be generated sequentially and at proper time intervals in accordance with a standardized system. RAM's (DRAM and SRAM) which are memory structures developed for electronic computers are characterized by being directly accessible and directly addressable, thus having a higher freedom of flexibility in the access and use of stored information. As used in video signal processing, however, it is necessary to direct an address for every bit of data to be stored or readout from such memory structures.
On the other hand, a FIFO memory (First-In First-Out Memory) type is favorable for removing such a defect in the storage and access of data bits requiring individual addresses for each bit, where the first data item deposited in a queue of data items is to be the first one reached in processing. So far however no FIFO memory having a sufficiently large storage capacity and operating at the high speed necessary for a TV display has been available. A digital type CCD memory to some extent is acceptable for this purpose of sequiential storage and access of data, but it is generally not possible to use a CCD memory in a high speed operation or to perform simultaneous readout and writing of information with respect to, with the result being a restricted memory system of limited versatility.
In general, one approach toward adapting a RAM to video signal processing has taken the form of adding a circuit to a DRAM or an image processing-suited VRAM for controlling the address and refresh functions such that functions similar to those of a FIFO memory can be performed. The RAM function proper of the memory structure alone, during video signal processing, has not permitted the memory system to operate as other than a RAM, thus requiring a composite memory construction with the combined functions of a RAM and a FIFO memory, accompanied by an increase in the number of circuit elements. Such a composite memory structure also has difficulties as to reliability and would be more expensive as well. Because of these factors, the development of graphics-dedicated memory with the intention of reducing the functional burden of peripheral circuits, did not evolve as a complete FIFO memory device, but instead as a memory device designed for a particular purpose. This type of memory development is disadvantageous because the development of a special-purpose memory does not permit as much freedom in design as would be desirable.